Verification IP for HBM

Synopsys® Verification IP for HBM provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of HBM based designs.

Memory Model Certification

Synopsys provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. Synopsys’ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. Synopsys Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of Synopsys Memory VIP.

Highlights

  • Native SystemVerilog/UVM
  • Runs natively on all major simulators
  • Runtime JEDEC and vendor part selection
  • Verification plan and coverage
  • Built-in protocol checks
  • Verdi® protocol-aware debug and performance analyzer
  • Back door memory access
  • Bypass, fast-memory initialization
  • Trace files and debug ports
  • Multi channel environment
  • Error injection and exceptions
Verification IP for HBM

Features

HBM3 + -

All commands including refresh management commands

All Test instructions

All HBM3 trainings:

  • DCA/DCM
  • Wdqs2ck training
  • Loopback Test Modec45

Data skew and Data bus inversion

Command and Data parity

All mode register support covering all settings

Other features:

  • Optimized refresh
  • Delayed refresh rate change
  • Adaptive Refresh management (ARFM)
  • WDQS Oscillator
  • Error Check & Scrub
  • Self-repair
  • Mode register configuration via backdoor and via MR DUMPSET Command

All commands:

  • MRS, ACT, WR, RD, PRE, REF
  • PDE-PDX, SRE-SRX

All Test instructions

Loopback Test Modes:

  • AWORD/DWORD Write MISR
  • AWORD/DWORD Write Register Mode
  • DWORD Read Register Mode
  • DWORD Read LFSR Mode
  • AWORD/DWORD Write LFSR Compare Mode

Data Bus inversion and Data Masking

Command and Data parity

All mode register support covering all settings

Other features:

  • Target Row Refresh
  • Mode register configuration via backdoor and via MR DUMPSET Command

Clock Jitter

RDQS Jitter

RDQS Duty cycle adjustment

Callbacks for data corruption

Static and dynamic reconfiguration for timing and configuration settings

Data Eye damage

Board delay modelling

Skew Support (twdqs2dq_i and twdqs2dq_o)

Functional, checker and timing coverage

Is_valid checkers

Hierarchal Verification Plan

Tested with vendor part numbers

Analysis port for score boarding

Verdi protocol Analyzer and Performance Analyzer

Contact the VIP Team