Synopsys announced last Monday a breakthrough in verification, system validation and embedded software development technology. There was good coverage, for example in Ron Wilson’s and John Blyler’s blogs. One main question we got from users and the press was about how this all works together with the virtual platforms we provide as part of our Innovator environment.  John Blyler asked it flat out “One other question: How will this hardware prototyping platform eventually work with Synpopsys software (virtual) prototyping tool – from the Virtio acquisition?”

We have demonstrated interfaces to hardware based solutions for a while with Eve and Palladium. Synopsys now has the three necessary technology components for hybrid prototypes in house and are preparing for demonstrations with various customers. Starting on the hardware side, physical interfaces must be provided to connect the actual hardware prototype to the workstation running the simulation. PCI Express is a common solution here. Second, data must be transported using an agreed upon protocol between the software and hardware worlds. SCE-MI has become a standard in this domain. Finally, for conversion from the transaction-level model to the transport interface, transactors are necessary to translate high-level protocols like AXI, OCP and AMBA.

In addition we have talked to about 25 customers worldwide (yeah, I made it to be United 1K for the tenth year now) to understand their needs. We were able to condense the use models of virtual platforms and FPGA prototypes to five main use models:

• RTL Reuse and Architecture Verification: Given the high IP re-use rates in today’s design, RTL may exist from previous projects or may be acquired. While more and more IP users request high-level models as part of an IP purchase, it may not always be available. Hybrids of virtual platform and FPGA prototype allow a virtual platform to re-use existing RTL and avoid modeling effort of potentially complex IP blocks. Given that FPGA prototype execution is essentially cycle accurate, it also increases overall fidelity and allows to swap out the virtual model with RTL to verify that architecture decisions were correct.
• Accelerated Software Execution: Due to FPGA implementation optimization for algorithm execution and not processor implementation, software typically runs on workstations and virtual processor models faster than in FPGA prototypes. Hybrids of virtual platform and FPGA prototype with processor models on the workstation allow overall faster execution while maintaining accuracy of accelerators and peripherals.
• Virtual Platform as test bench for FPGA prototype: Given that verification often starts at the pre-RTL level for validation purposes, system-level development efforts can be re-used for the actual RTL verification. Hybrids of virtual platform and FPGA prototype with the virtual platform acting as testbench avoid duplicate efforts and enhances model re-use
• Joint system environment connections: For popular interfaces like USB and SATA virtual platforms already provide real-world and virtual I/O interfaces, for example connecting to physical USB devices. In addition a daughter cards in FPGA prototypes provide real world I/O with interfaces to real life streams like the wireless physical interfaces. Hybrids of virtual platform and FPGA prototype with real world I/O on both sides allow real world stimulus to be used where most appropriate.
• Virtual platform “Virtual ICE” connected to FPGA prototype: Re-use of the virtual development environment running in a virtual platform including for example disks, USB virtualization, visualization etc. allows better access to FPGA prototypes and decreases set-up time. Hybrids of virtual platform and FPGA prototype with the virtual platform executing the development environment avoid additional development efforts, allow the FPGA prototype to be kept remote and increase familiarity for software developers who often prefer to just see a keyboard and screen

Over the next couple of weeks and month we will be demonstrating this flow using Innovator virtual platforms connected to the ChipIT FPGA prototypes using the SCE-MI 2.0 interface.

If you are interested in more information or a demo please don’t hesitate to contact me directly or contact the system-level design team directly.