| |
|
|
| |
| Interact with other users! |
| Forums |
 |
SynopsysOC Discussion Forum
an open community where low power and verification design challenges are discussed.
|
| |
| |
| VMM for SystemVerilog Companion Guide |
 VMM for SystemVerilog Companion Guide is a handy quick reference for users of the Verification Methodology Manual (VMM) for SystemVerilog, a professional book co-authored by verification experts from ARM Ltd and Synopsys, Inc and published by Springer Science and business media. DOWNLOAD
|
| |
| Featured Videos |
 DesignWare VIP Detailed Usage
Presenter: Darrin Mossor, Synopsys
The Synopsys DesignWare Verification IP for AMBA 3 AXI provides an effective method of verifying AMBA 3 AXI protocol based designs. This session provides in-depth technical insight into working with the Verification Methodology Manual for SystemVerilog compliant and “AMBA 3 Assured” DesignWare Verification IP. The DesignWare Verification IP for AMBA 3 AXI includes master, slave, monitor and verification interconnect components with each supporting all the AMBA 3 AXI address, data widths, and protocol transfer and response types. The session documents how this full featured command set can be utilized to create both a directed test transaction environment as well as how to leverage the coverage driven, constrained random verification interface support.
|
| |
| Featured AMS Verification Webcast |
 Predictable AMS Performance using Full Chip Mixed-Signal Verification
Discovery-AMS, with the inclusion of best-in-class fastSPICE engines, enables the designer to verify transistor level effects like signal integrity and power consumption in sensitive digital or analog blocks. Discovery-AMS is targeted at both digital-on-top and analog-on-top design styles.
|
| |
| |
| Featured White Papers |
| Functional Verification |
Managing Functional Verification Projects Meeting the challenges of
high-level verification in today's SoC
This white paper, from Synopsys Professional Services, explains key factors that affect verification productivity and provides recommendations for optimal deployment adoption of advanced verification languages and methodologies. In addition, common bottlenecks that impede the successful migration to advanced verification methodologies are identified with suggestions for how to resolve them.
READ MORE |
| |
| AMS Verification |
A High-Performance Timing Simulation Methodology for Multi-Processor SoCs
Experiences in timing simulation of 6-core 20-million gate MP-SoC are discussed. The combination of tool and methodology enhancements enabled the existing 32-bit compute farm to be used for most verification scenarios. Gains of about 4X in run-time with a 2X smaller memory footprint were obtained, even for full-timing simulations.
(SolvNet ID and Password Required)
READ MORE
|
| |
| |
| Interact with technical experts! |
| |
| Book Club Verification Methodology Manual |
 Verification Methodology Manual for SystemVerilog
The Verification Methodology Manual for SystemVerilog is a blueprint for system-on-chip (SoC) verification success. The book documents advanced functional verification techniques used by industry experts to validate complex SoCs.
Go to the SynopsysOC Forum to discuss the VMM manual.
|
| |
|
|
