| White Papers |
Advanced Stimulus Generation with DesignWare® Verification IP and Verification Methodology Manual VMM for SystemVerilog
This paper discusses advanced verification techniques using DesignWare VIP and VMM for SV to build a sophisticated constrained random testbench capable of advanced stimulus generation. Exceptions and scenario generation are the two main topics discussed. |
|
Assertion Specification and Usage Requirements
This article provides some background on assertions and their value as part of a DFV process, and discusses different methods for assertion specification. |
|
Successful Mixed-Language Code Coverage with VCS
This article provides a basic guide for using VCS code to coverage metrics for design verification on Verilog, VHDL, and mixed designs. |
|
Applying CRV to Microprocessor Verification
This paper proposes an object-oriented solution to address key verification challenges in processor instruction stimulus that have previously made high level verification languages somewhat unattractive to this unique application domain. |
|
Accelerating Functional Closure: Synopsys Verification Solutions
This paper focuses on practical aspects of the verification process that can help reduce the time taken to reach functional closure. |
|
Verification IP Qualification and Usage Methodology for Protocol-Centric SOC Design
This paper discusses a structured methodology for evaluating VIP along the four dimensions of VIP quality - Authoring Process, Verification, Maturity and Vendor Capability - to ensure that the selected VIP will deliver on the promise of shorter verification cycle time and greatly improved product quality. |
|
Integrating System Models in a RVM Leveraged Environment
This paper examines several different methods for system model integration into an RVM environment. |
|
Automated Response Generation for IP Based Subsystem Verification
This paper describes a method for producing automated contrained random responses to write and read requests in support of functional verification of an IP based subsystem. This approach can reduce the overall effort expended on verification by enabling full use of constrained random verification techniques. |
|
SystemVerilog for e Experts – Understanding the Migration Process
This document identifies the major differences between the e language as defined by the IEEE P1647/D6 draft standard and SystemVerilog language as defined by IEEE Std. 1800™ 2005 standard. It explains the semantics of these differences and, where relevant, presents how similar functionality can be obtained using SystemVerilog. The document concludes that any verification environment based on e could easily and efficiently be implemented in SystemVerilog. |
|
Transaction-Level Modeling: SystemC or SystemVerilog?
This article takes a practical view of transaction-level modeling. It looks at two broadly supported, industry-standard languages, IEEE 1666 SystemC and IEEE 1800 SystemVerilog, and explores how they support the concepts of TLM. |
|
Applications of Hybrid RTL Formal Methods to Block Level Verification
This article highlights how coupling the Design for Verification (DFV) methodology with advanced hybrid RTL format tools like Magellan™ can dramatically improve verification productivity and increase the confidence that a design is functionally correct. |
|
Verify More in Less Time with VCS
This paper describes how the VCS® RTL solution from Synopsys runs up to 5X faster than traditional approaches, enabling fundamental improvements in verification efficiency and thoroughness even for the most complex system-on-chip (SoC) projects. |
|
