Resource Center: Case Studies
Synopsys DesignWare® Ethernet VIP Saves Two Months Time to Market on Commex Chip
Commex Technologies, Inc. is employing novel concepts in the design of its chips and an equally novel approach for bringing them to market quickly. Synopsys VCS Native Testbench (NTB) and the VMM methodology provided a trustworthy foundation for the firm’s verification environment and DesignWare Ethernet verification IP integrated easily into the environment, allowing Commex to save substantial engineering costs and time to market on its first product. |
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Verification of a NET+ARM Processor with VCS and Vera
Brad Hollister, Verification Lead at NetSilicon, describes the development of a processor for networking operations. The chip was functionally correct on first silicon, satisfying the project goals and meeting the market window. |
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VCS Provides High Performance Needed for Verification of Complex Wireless Chipset FPGA and ASIC Designs
Darcy Poncsak, Verification Lead at WaveSat, describes that how, with the faster simulation speed of VCS, WaveSat was able to complete the 802.16-2004 design on schedule. |
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Gennum Adopts VCS™ MX to Optimize Their Complex Verification Methodology
Dave Simmons, Director of Video Product Development at Gennum, discusses Synopsys’ VCS MX simulation platform which reduced the time and manpower requirements for verification of Image Processing ASICs. |
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STMicroelectronics; Take the Next Productivity Leap
Remi Francard and Franco Toto of STMicroelectronics discuss how hybrid-formal verification ensures that design teams achieve first-pass silicon success while reducing development time. |
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Sun Microsystems: Using Magellan to Diagnose Post-Silicon Bugs
Catherine Ahlschlager and David Wilkins from Sun Microsystems discuss how the combination of formal analysis for complex blocks and a sophisticated chip-level simulation is highly effective for the verification of their UltraSPARC Processors. |
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Hifn: Using Vera in the Lab
K.C.Buckenmaier, Changyong Yang of Hifn and Chris Spear of Synopsys discuss how an estimated 6 -12 engineer-months was saved by reusing in the lab an extensive Vera environment and infrastructure that was created to test a device. |
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