Resource Center: Functional Verification Videos
SystemVerilog Video Seminar Series
This video seminar provides a rich supply of information to help you transition to a standards-based verification methodology built on SystemVerilog. |
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ARM / SYNOPSYS: Accelerate AMBA 3 AXI Design Verification with DesignWare
In these four in-depth videos, ARM and Synopsys show how Synopsys DesignWare® verification IP allows you to rapidly validate your AMBA® 3 AXI™ protocol-based designs. The Synopsys DesignWare solution reduces risk by increasing functional coverage and ensures successful and rapid time-to-market. Design starts are ramping up for AMBA 3 AXI and it’s looking like the next de facto standard high speed bus architecture.
- AMBA 3 AXI The Protocol Advantage
- Hardware Platform-Based Design
- Synopsys/ARM Verification Methodology
- DesignWare VIP Detailed Usage
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Introduction to Assertion-Based Verification
Ever increasing design size and complexity are stressing current verification methodologies. Now, more than ever, there is a pressing need to adopt a Smart Verification environment with reusable assertions. This technical webcast shows a powerful new approach to functional verification that dramatically improves the efficiency of verifying intended design behavior, detecting bugs and fixing bugs throughout the design process. The webcast will show you how to quickly and easily start using Assertion-Based Verification on your current designs |
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Introduction to SystemVerilog
With designs continuing to increase in size and complexity, today's design and verification methodologies are being stressed to the breaking point. Many users have come to realize that they can't continue to describe their designs adequately in Verilog while using separate languages for verification and multiple tools for simulation, coverage analysis, testbench and formal verification. This technical webcast will introduce the new Accellera SystemVerilog 3.0 standard, and show how it enables a powerful new methodology that brings design and verification engineers under one language "umbrella". We will show new design constructs and how Synopsys' VCS™ Smart Verification Platform brings all of these capabilities into a single unified environment to maximize productivity of both design and verification teams. |
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Static Verification with Leda in Discovery Verification Platform Web Seminar
Come join us for a one-hour live webcast to see how Synopsys addresses these design verification problems with LEDA, a programmable mixed language RTL and gate design checker in the Discovery Verification platform. All design and verification engineers stand to benefit as this technology finds complex design bugs while writing code, improves performance of tools and flows and helps design reuse. |
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