'Off by Design' architectures curb energy waste
SCD Source - Srikanth Jadcherla (Synopsys) - 3/25/2008
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Migrating Complex Networking ASIC Verification Environment to SystemC and SystemVerilog
IC Journal - Srinath Atluri, Nimalan Siva, Anant Sakharkar (Cisco) and Rebecca Lipon (Synopsys) - 3/18/2008
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Verify SoCs Faster And More Predictably With SystemVerilog And Constrained-Random Stimuli
Electronic Design – Henry Angulo et al. - 3/5/2008
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VMM application packages: the next level of productivity
EDN - Janick Bergeron (Synopsys) - 2/21/2008
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Three verification improvements boost functional coverage
SCD Source - Alfonso Íńiguez and Shankar Hemmady - 2/20/2008
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Coverage metrics not enough, verification experts say
SCD Source - Richard Goering - 2/7/2008
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Nightmares in Functional Verification
Chip Design Magazine, Ed Sperling
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Applying Constrained-Random Verification to Microprocessors
EDA DesignLine - Jason C. Chen - 12/10/2007
The CRV approach outlined offers an effective way to overcome the limitations of traditional directed tests for verifying microprocessors by taking advantage of object-based randomization using constraints. |
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Verification Avenue
Nov 2007
The Synopsys Technical Bulletin for design and verification engineers
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Future Verification Appears Uncertain
Chip Design – Geoffrey James – Oct/Nov 2007
A funny thing happened on the way to 45 nm. Verification- once the sleepy backwater arena of the EDA industry- suddenly became massively important. |
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Verification Avenue
October 2006
The Synopsys Technical Bulletin for design and verification engineers. |
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SystemVerilog reference verification methodology: Introduction
EE Times - Thomas Anderson, Janick Bergeron, Eduard Cerny, Alan Hunter, and Andrew Nightingale - 3/27/2006
This is the first in a series of four articles outlining just such a solution: a reference verification methodology enabled by the SystemVerilog hardware design and verification language standard. |
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SystemVerilog reference verification methodology: RTL
EE Times - Thomas Anderson, Janick Bergeron, Eduard Cerny, Alan Hunter and Andrew Nightingale - 5/1/2006
This is the second in a series of four articles outlining a reference verification methodology enabled by the SystemVerilog hardware design and verification language standard. |
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Transaction-Level Modeling: SystemC and/or SystemVerilog
SOCCentral - Rindert Schutten and Janick Bergeron – 3/6/006
By bringing SystemC and SystemVerilog together in a single modeling and verification environment, architectural exploration and tradeoffs can be made before the final hardware-software partition is settled. |
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Synopsys Offers Verisity Migration
EETimes – Richard Goering - 2/14/2005
Synopsys' Native Testbench (NTB) migration service promises to convert Specman Elite verification environments to VCS, and to include tool, language and methodology training. |
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Synopsys Woos Verisity Users with Migration Service
Electronic News - online staff - 2/14/2005
For users of Verisity's Specman Elite testbench product wishing to migrate to Synopsys' popular VCS RTL verification tool, Synopsys has begun a Native Testbench (NTB) migration service |
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Coverage is the Heart of Verification
EE Times - Thomas L. Anderson - 2/14/2005
Managing verification requires knowing, at every step, which coverage results are acceptable, which need improvement, and which bug-finding technology should be used next to improve coverage. |
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How to Choose a Verification Methodology
EEdesign.com - Rangarajan (Sri) Purisai - 7/09/2004
In this article some trade-offs that companies could make in order to adopt best-in-class tools and technologies to achieve long-term success are presented. |
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Advanced Block-Level Bug-Hunting with Assertion-Based Verification Methodology
SoC Explorer - Alessandro Fasan – 6/1/2005
There is no reason to try to exercise coverage targets that are unreachable, and the tool clearly reports these because of its built-in, high-capacity formal engines. |
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Achieving the Next Productivity Leap
Chip Design Magazine - Remi Francard and Franco Toto - January 2005
Hybrid-formal verification ensures that design teams achieve. |
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ESL-based flow eases complex SoC design
EE Times - Rindert Schutten - 6/07/2004>
Although definitions vary, most engineers agree that ESL-based development comprises methodologies and tools that deal with design complexity through abstraction, a well-established practice in engineering. |
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