Resource Center: Technical Papers
Backend Methodology and Techniques for a Multi-Protocol Mixed Signal IP Design
ASIC I/Os have been evolving from relatively slow parallel interfaces to high-speed interface links. This evolution has created a difficult design problem for ASIC manufacturers that is increasingly being solved by purchasing rather than developing the required I/O IP. This paper focuses on the back-end challenges and solutions in development of a physical layer, mixed-signal IP (PHY) that supports three standards: PCI-Express, SATA and XAUI. |
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Techniques in Verification of Mixed-Signal & SoC Designs Using NanoSim Design
Shrinking process geometries, higher frequencies and increasing design complexity are stretching the limits of design tools and methodologies. This paper illustrates how NanoSim has evolved into the most comprehensive solution for verification of mixed-signal designs and SoCs. |
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NanoSim: A Next Generation Solution for SoC Integration Verification
As process technologies continue to advance below 100 nanometers, the cost of leading-edge SoC design time plus time-to-volume pressure will no doubt continue to rise. This paper discusses the feature of NanoSim and highlights how its technology is easy to adopt into any transistor-level verification flow and addresses multi-level mixed-signal verification needs. |
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LG Electronics: Using NanoSim for Video Signal Digitizer Design
Currently, video signal digitizer for scalar (format converter) is commonly used with LCD monitor, PDP panel, DMD projection and other signal processing applications. This paper discusses using NanoSim to save simulation time for video signal digitizer. |
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Atmel: Full Chip Verification Using NanoSim
This paper describes a methodology using NanoSim to debug and verify the operation of an embedded micro controller system containing a number of mixed analog-digital building blocks. A number of problem areas are identified, and solutions utilizing NanoSim are presented. |
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SUNPLUS: Using NanoSim for Mixed-Level Simulation
This presentation discusses the transistor level simulation impact of using NanoSim eNIV for mixed-level simulation. |
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Motorola: Verification of Large Mixed-Signal SoC Using NanoSim and VCS
This paper addresses the challenges of mixed-signal SoC verification and detail a methodology to accomplish the task, using NanoSim and the NanoSim-VCS co-simulation environment. The results achieved with this verification methodology on a mixed-signal SoC design are also presented. |
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ST Microelectronics: NanoSim in Memory Characterization Flow
NanoSim timing and power characterization results are within 5% of Spice when properly tuned to the design. Synopsys has customized netlist syntax, device model interpretation, and wave file format to meet STMicroelectronic’s special requirements. |
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Teradyne + ASIC North: Mixed-Signal Verification Using NanoSim and VCS
This paper discusses a mixed-signal verification methodology that uses VCS and NanoSim to verify a mixed-signal system-on-a-chip (SoC) device. This verification methodology enabled integration issues to be discovered earlier in the design process and avoided costly re-spins. |
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VIA: NanoSim and VCS Application for SoC Design
This paper demonstrates the conventional Synopsys TLD flow and proposed NIV flow in circuit simulation . |
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Broadcom: 500 Mb/s DDR2 SDRAM Analysis using HSPICE®
Timing constraints, signal integrity and power integrity issues continue to grow in complexity with every new signaling standard and DDR2 SDRAM proves no exception. This paper presents several HSPICE techniques used to design and analyze a 128-bit, 500Mbps, DDR2 interface. |
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| White Papers - (SolvNet ID and password required) |
PLL Noise Analysis with HSPICE RF
This white paper describes a procedure for efficiently extracting key noise
measurements for a phase locked loop using HSPICE RF. The procedure has been updated to take advantage of several new and unique capabilities in HSPICE RF that can be used to accurately predict PLL steady-state and phase noise characteristics. |
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HSPICE Testbench Technologies for Analog & RFIC Design
Analog and RF circuits must be designed to meet a diverse set of specifications spanning a broad range of time-domain and frequency-domain performance goals. This paper describes HSPICE’s new analysis capabilities which are fine -uned to best support today’s rigorous analog and RFIC design flows. |
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Ring Oscillator Phase Noise Simulation
This paper discusses how to simulate a ring oscillator with HSPICE RF, determine its phase noise, and improve its phase noise performance. This paper also compares different ring oscillator architectures and their phase noise performance in HSPICE RF simulation results. |
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HSPICE with Verilog-A, Productivity Boosts and Automating Waveform Analysis in CosmosScope
This presentation introduces and demonstrates the benefits of HSPICE's new Verilog-A capability for novel applications in analog circuit design and characterization. |
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