Resource Center: AMS Webcasts
Predictable AMS Performance using Full Chip Mixed-Signal Verification
Over 70% of SoC designs require more than one costly respin. Two significant causes of failure are errors introduced at the mixed-signal interface and analog tuning issues. Verification at the block level is no longer sufficient! Analog blocks are designed at the transistor level and digital blocks at the gate level requiring a mixed-signal verification methodology. Discovery-AMS, with the inclusion of best-in-class fastSPICE engines, enables the designer to verify transistor level effects like signal integrity and power consumption in sensitive digital or analog blocks. Discovery-AMS is targeted at both digital-on-top and analog-on-top design styles. Blocks can be modeled in digital or mixed-signal HDL languages such as VHDL or Verilog-AMS, accommodating any design size from Big-A/ Big-D to Little – A/ Little-D. |
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HSIMplus Beyond Fast SPICE Simulation
Fast-SPICE simulation in the past was limited primarily to functional verification, because the gains achieved in simulation performance required giving up on SPICE accuracy. HSIM® goes beyond traditional Fast-SPICE by integrating HSPICE® device models, the industry’s golden standard for accuracy, with a high-capacity hierarchical simulation engine for designs containing millions of transistors. HSIMplus™ provides additional capabilities for performing full-chip simulation with parasitics; analysis of dynamic IR drop, electro-migration, and signal-net coupling effects. |
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Robust SI Analysis of a DDR2 Interface with HSPICE
For years designers around the world have trusted HSPICE for their signal integrity simulation needs. For video memory and many other applications, increases in chip and board speeds over the last few years have created significant and widespread demand for accurate signal integrity analysis. This tutorial walks through the setup, simulation and analysis of a Synopsys DDR2 memory interface highlighting HSPICE’s signal integrity analysis features. |
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Predicting PLL Phase Noise & Jitter with HSPICE RF
Due to today’s ever increasing data rates, phase noise and jitter specifications are now critical aspects of modern phase-locked loop design. Accurate predictions of PLL noise are possible through circuit simulation, but the steps required to do so are often shrouded in mystery or considered too challenging to undertake. This tutorial outlines a procedure for efficiently extracting key phase noise and jitter measurements for phase-locked loops using many of the unique simulation capabilities of HSPICE RF. |
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