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Analog/Mixed-Signal Verification
Increasing Analog and Mixed-Signal Content in SoC designs is driving the demand for High Capacity, High Performance, SPICE Accurate AMS Verification. Nanometer issues such as reliability and process variation necessitate the need for advanced analysis capabilities and methodologies to prove that designs not only meet specifications but are robust and to ensure profitable yield. SynopsysOC is an online community that facilitates discussions addressing advanced methodologies in the area of Analog / Mixed-Signal Verification and provides valuable resources and technical perspectives from industry experts.
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SynopsysOC Discussion Forum
an open community where low power and verification design challenges are discussed.
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| Featured Analog Verification Webcast |
 Predictable AMS Performance using Full Chip Mixed-Signal Verification
Discovery-AMS, with the inclusion of best-in-class fastSPICE engines, enables the designer to verify transistor level effects like signal integrity and power consumption in sensitive digital or analog blocks. Discovery-AMS is targeted at both digital-on-top and analog-on-top design styles.
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| Featured White Papers |
A High-Performance Timing Simulation Methodology for Multi-Processor SoCs
Experiences in timing simulation of 6-core 20-million gate MP-SoC are discussed. The combination of tool and methodology enhancements enabled the existing 32-bit compute farm to be used for most verification scenarios. Gains of about 4X in run-time with a 2X smaller memory footprint were obtained, even for full-timing simulations.
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