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Resource Center: Technical Papers
Power Hungry? Strategies to Trim Your Chip's Appetite
Part 1: Overview, Analysis, Architectural Solutions
This white paper, from Synopsys Professional Services, is Part One of the two-part series that provides an overview of the topic of SoC power management and describes methods for estimating and analyzing power consumption. Using insights from a pool of industry talent, including Synopsys R&D engineers, consultants, and customers with design experience at 90nm, 65nm, and 45nm, Part 1 of this series provides a full description of power-related issues and the requirements for early power planning, starting at the architectural level. Part 2, to be subsequently published, will describe details of power-management methods, with an emphasis on the growing importance of leakage power in SoCs. |
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Decoupling Capacitance Estimation, Implementation and Verification: A Practical Approach for Deep Submicron SoCs
The problem of dynamic variations in supply voltage and the related impact on chip performance is a major issue facing today’s DSM SoC design teams. Through careful design of the power supply network, correct chip functionality can be ensured. This paper describes practical implementation approaches and verification techniques developed by Synopsys Professional Services. |
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Sleep Transistor Design and Implementation – Simple Concepts Yet Challenges to be Optimum
Optimum sleep transistor design and implementation are critical to a successful power-gating design. This paper describes a number of critical considerations for the sleep transistor design and implementation including header and footer switch selection, sleep transistor distribution choices and sleep transistor gate length, width and body bias optimization for area, leakage and efficiency. |
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Power Management In Complex SoC Design
The rise in SoC size and speed, as well as the increase in leakage current in Very Deep Sub Micron (VDSM) process technologies, have led to power consumption challenges across a broad range of designs that have not been viewed as supply limited or "low power" designs. |
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Power Integrity for SoCs: Power Planning and Signoff Flows
Power integrity has become a crucial part of SoC design flow because power-related issues can affect chip timing and even lead to complete device failure. This paper provides a power-planning methodology to solve this dilemma. |
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A Practical Methodology for Calculating Acceptable IR Drop Targets in Advanced VDSM Design
Smaller process geometries have led to a dramatic increase in problems due to "IR drop." The purpose of this paper is to determine what an acceptable IR target should be. |
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Implementing an End-to-End Low-Power Multi-Voltage Methodology
Power reduction has become a ubiquitous design goal for practically every design application, whether mobile or not. Reducing power consumption in chips enables better, cheaper products to be designed and power-related chip failures to be minimized. The design goal is simple: achieve the lowest possible power and area that will support the specified performance. This paper explains the multi-voltage concept and the detailed requirements for designing with a multi-voltage design flow. |
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