Low-Power Panel: Shaken or Stirred by Low Power Design Challenges?
Industry recognized low power experts from ARM and Synopsys will share case studies and step-by-step recommendations to achieve low-power silicon success. The panel will discuss solutions to static and dynamic power challenges, including MTCMOS state retention power gating, dynamic voltage and frequency scaling, as well as power network design and analysis. |
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Design and Verification of Ultra Low Power SoCs with ARM Cores
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Maximize Virtual Platform ROI by Efficient Model Development
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Managing Power in 45nm and 65nm Designs
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Leakage Mitigation in ARM Processor Based Systems
Original Webcast: December 18, 2007 |
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Seminar: The Future of Low Power
Synopsys Fellow Mike Keating addresses the long term (3-5 yr) issues in design for low power. Included in his talk is a discussion of some key technologies that affect, or are affected by, low power design goals. Finally, the implications for the design methodology of the future are discussed. |
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Scaling the Power Wall
Dr. Jan Rabaey
Donald O. Pederson Distinguished Professor, University of California Berkeley
Many approaches have been introduced to address the concerns regarding both active and standby power. Yet, none of these provides a persistent answer that extends into the foreseeable future. Going to the next step will require us to venture in some new directions, some of which may be quite unorthodox. In this presentation, we will browse some of the opportunities that may arise through ultra low-power design and outline some potential solutions. |
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Power Reduction: Is it Time to Re-examine Asynchronous Design?
Dr. Robert Damiano
Synopsys Fellow and Vice President, Advanced Technology Group
This presentation will introduce some existing methodologies for designing ICs that are free of global clock distribution networks. These ICs have lower power and are less sensitive to variation compared to their conventional counterparts. Research opportunities for new tools in this area will also be addressed. |
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Engineering Notebook: Low Power Interview
This episode contains an interview with low-power guru Jason Binney (a seasoned low-power engineer) and covers topics in advanced semiconductor design. Jason discusses design implications of new technology choices, new legal considerations and low-power issues in consumer electronics. And the future of batteries is in methanol? Hear it all and more in the interview.
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Unified Power Format (UPF) interview at DAC on YouTube
This interview by Richard Goering of EE Times interviews Magma, Mentor and Synopsys who collaborated to sponsor the Unified Power Format booth at DAC. |
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Synopsys Power Management Solution
Delivering the lowest power with the lowest risk, this end-to-end solution is proven and trusted by market leaders. It boosts designer productivity via consistent power predictability throughout design implementation and verification. Utilizing Accellera's Unified Power Format (UPF) standard the power intent is defined once and used throughout the flow. |
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Advanced Techniques with Synopsys DesignWare® Virtual Platforms
This demo tours four advanced capabilities of Synopsys Virtual Platforms: system modeling capabilities, power modeling and power estimation, multicore debugging and Virtual Platform customization. Virtual Platforms have the capabilities of modeling frequency scaling, voltage scaling, very complex power management IC’s which typically sit next to the main system on a chip, clock gating, different power domains, different rail voltages and more. |
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