Synopsys Cloud
Cloud native EDA tools & pre-optimized hardware platforms
Request a Free Trial →
Table of Contents
My name is Keith Redmond and welcome to my blog series, “Verification Viewpoints." In this series, I will be posting about a number of processes and flows that have helped make our verification team at Synopsys more productive.
As we know, there are a couple of major reasons why teams look to increase productivity:
- Getting more done - Since verification teams are often stretched thin, improving productivity results in reduced stress for the team and generally a higher quality of work.
- Improved employee satisfaction – When we talk about improving productivity, what we’re trying to do overall is reduce the amount of time team members spend on menial, repetitive, or frustrating tasks. This allows them to focus on what they really want to and enjoy doing – innovating and solving real problems. In the end this is a win for both employees and the company.
Thus, our goal should always be to have the verification team focused as much as possible on problems that cannot be solved by machines, tools, or automation.
About me
I’ve spent my entire career doing either ASIC verification or software. Most of my experience been working as a technical lead on ASIC verification, but my time in software provided me with valuable hands-on experience with processes, techniques, and design patterns pioneered in the software industry that are very applicable to verification.
As a verification lead, I’ve seen the positive impact automation and efficiency improvements can make, and conversely how frustrating it is when a fragile testbench causes endless time spent on debug and maintenance. My goal with this blog is to highlight pitfalls you may encounter during the verification process and inspire you with solutions to overcome those pitfalls. The solutions I will discuss in this series are certainly not the only way to do things, they are meant to serve as examples that have worked for us.
My assumptions of you
If you’re reading this blog series I’m going to be assuming a few things about what your team does.
- I’ll be assuming you work on a digital verification team, working closely with the digital design team. I’ll assume that the verification work proceeds in parallel with the digital design, so both design and verification are changing at the same time. I’ll also assume that you’re working on a pre-silicon team or FPGA.
- I’ll assume you’re using a constrained-random coverage-driven environment, typically build using the UVM library.
- The focus of these blogs will be on improving productivity for the dynamic simulations. While static verification (formal) is also an important tool, it will not be the focus of this blog series (at least for now).
Please keep in mind that if some (or all) of the assumptions above don’t align with your current activities/role, my hope is that you may still be able to glean some wisdom from these posts, but understand they will be written from the perspective of a digital verification team.
What you can expect from these blogs
Here is an outline of the topics that I intend to cover in this blog series:
- Shift left with sanity testing
- Continuous Integration in a verification setting (using Jenkins)
- Using Baselines to simplify failure reproduction and workspace state sharing across team members
- Importants and contents of good regression reports
- Testbench design philosophies and patterns
- And more...
Conclusion
I hope you enjoy reading this blog series!
Lastly, I encourage you to visit our website for more detailed information on Synopsys’ industry-leading verification and IP solutions.
Continue Reading
