Hello Everyone,

I suppose that I should just declare today “Hail Britannia” day here at Analog Insights. Hopefully, you have already read my post from earlier today on “Spicing things up”… with a British accent. Maybe you also have noticed my Blogroll over on the the left side of this blog page, with the link to my friend Simon Young’s blog at “All About EDA“. Well, to further add to today’s “British Invasion“, I just came across another interesting technology blog with the unlikely name of “Hacking Cough“. Maybe that’s a reference to a Monty Python skit that I missed… I don’t know.

In any case, the author of Hacking Cough (Chris Edwards) wrote recently on one of my favorite issues - SPICE accuracy. You can read about it in “EDA’s Acceleration Option“. As it turned out, that article was an interesting precursor to my recent post on simulation accuracy, Simulation accuracy… it’s the silicon, ******!

I was compelled to join the discussion over at “Hacking Cough”, and I thought I would share my comments with you here as well:

_______________________________________________________

Hi Chris,

Your article popped up in my Google search widget today, due to Simon Young’s reference to my Analog Insights blog. I also found your original article to be very interesting, especially the point about SPICE accuracy and single-precision. There is so much mis-information being published on the topic of SPICE accuracy these days that it has become one of my pet peeves. One of my recent articles on the topic is Simulation accuracy… it’s the silicon, ******!

If you talk about SPICE accuracy you have to start with HSPICE, which is the incumbent gold-standard that everyone else tries to compare to. As was noted in Simon’s comment, since HSIM is part of the same Synopsys Discovery-AMS product family as HSPICE - it has the luxury of sharing the same gold-standard models.

The comment about how multi-threading model evaluation in SPICE can impact performance is valid, but why rely on a “secret sauce” when you can get the real thing from the trusted standard? You can read some of the latest news about how HSPICE has accelerated simulation through multi-threading here: Synopsys HSPICE Delivers Innovative Technology to Accelerate Circuit Simulation Performance. HSPICE provides more than just acceleration of model evaluation, by also accelerating analysis on multi-core platforms.

Finally, Yes - I can show how HSIM Fast-SPICE can give a designer even greater accuracy than SPICE. And it’s no “trick”! With all the misguided focus on simulator “accuracy” comparisons you will find that even designers will sometimes forget what the objective is… It’s the silicon! Not the simulation! HSIM and HSIM^plus can give a more accurate representation of the silicon in post-layout simulations, because SPICE is very limited in the capacity to handle the millions of parasitic elements that are introduced when you actually build a circuit.

Thanks for the opportunity to weigh-in on this important subject. I will definitely being watching your blog more in the future.

-Mike Demler

SPICE multi-threading SPICE accuracy Electronic Design Automation

Good Morning Everyone,

For those of you who are reading this in Europe, you may already be familiar with the publication New Electronics, which is edited by Graham Pitcher. I love their tagline - “The Design Cycle Fortnightly” - so British!

I was interviewed by Graham recently for an article that just came out today: “Spicing things up, how eda companies are taking analogue design beyond Spice simulation”, which you can download from the New Electronics website. If you have read some of my earlier posts concerning interviews with the trade press, you will know that I have had “issues” recently with editors who don’t get the story right after some of these interviews. But I am very happy to say that there are no issues here with Graham’s article. He captured the essence of some important issues that I wanted to highlight for his audience, and that we also focus on here:

1. The so-called “digital” revolution is enabled by analog, transistor-level designers, The World is Analog… or if you prefer… Analogue!
2. Analog design is hard and getting harder. Designers must often work in digital processes to meet the demands of lower cost integration with digital circuitry for portable, wireless, and consumer electronics applications.
3. Significant advances have been made in the analog designer’s #1 “go-to” tool: SPICE. Simulation speed has increased to keep pace with increasing design complexity. New analysis capability focuses on device reliability, variability, and parasitic effects.

I invite you to download the pdf of the article at this link → Spicing things up.

-Mike
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Hi All,

The registration page for Synopsys’ DAC events went live last week, with several AMS-related topics that I invite you to check out. I previously told you all about the AMS Breakfast panel discussion on Tuesday morning, June 10, focusing on the topic “AMS Verification and Moore’s Law… solutions for 45nm and beyond“. Registration for the breakfast is now open as well.

On Monday (June 9) through Wednesday (June 11), you have the opportunity of attending presentations in Synopsys’ Demo suites on:

• Mixed-Signal Circuit Design and Verification with Discovery™-AMS and Synopsys’ Custom Environment (twice a day)
  
• Transistor-Level Design Analysis and Sign-Off Using Star-RCXT®, HSIM™ and HSPICE®

You can also start off your day on Wednesday morning with another stimulating discussion at the Interoperability Breakfast. The topic for this year’s program is Raiders of the Locked Art: Opening the Treasure with Interoperable PDKs, which addresses the issue of custom analog design interoperability through OpenAccess.

I am also going to be in the Synopsys booth for another “Meet the Bloggers” opportunity. Come on by and say hello!

-Mike

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AMS verification

Design Automation Conference

Open Access

Transistor-level verification Star-RCXT

Hello Everyone,

The Design Automation Conference will take place this year in Anaheim-CA, on June 8-13. (OK… insert your own Mickey Mouse jokes here ________ )

I hope to see many of you at DAC, but if you were not planning to attend perhaps I can attract you with the Synopsys AMS Verification Breakfast that will take place on Tuesday morning, June 10th. The theme for this year’s panel discussion is “AMS Verification and Moore’s Law… solutions for 45nm and beyond“. If you have attended the AMS breakfast panels in the past, you know that they have been very interesting and entertaining affairs. This year we will explore the topic of AMS verification challenges, and how to address the issues that occur when “analog meets digital“. You need to go to this AMS Breakfast link to register, and those in attendance will have a chance to win a free Apple iPod Touch.

Our panelists this year:

Thomas J. Sheffler, PhD.
Sr. Principal Engineer
Rambus, Inc.

Jess Chen
Senior Staff Engineer
Qualcomm CDMA Technologies

Jeff McNeal
R&D Engineer
Synopsys IP Solutions Group

Henry Chang
Vice President
Designer’s Guide Consulting, Inc.

Following presentations by our panel of experts, you will have the opportunity for Q&A as well. It will be a great opportunity to network with colleagues who are active in the growing field of AMS verification, so I invite you to sign up today!

-Mike
Design Automation Conference AMS Verification analog digital

Hello Everyone,

Many of you may be familiar with the slogan that was created by Bill Clinton’s presidential campaign manager in 1992 - “It’s the economy, stupid”! James Carville created that message to keep the Clinton campaign focused on what he felt was the real issue at the time, so that they wouldn’t get sidetracked. Since that slogan became so memorable it has been re-used and adapted many times, and I think it is very appropriate to keep a similar message in mind when you are doing SPICE or Fast-SPICE simulation of your IC design.

“It’s the silicon, ******!” NOT the simulation!

OK, now I certainly don’t want any of you to stop using simulation, but I need to make what I think is a very important point here. I see many people get sidetracked by focusing on (what they think is) simulation “accuracy” when they should be focusing on the real goal; how accurately is your simulator predicting the behavior of the silicon? There is a HUGE difference.

Every designer knows that you are going to see a distribution of performance when you fabricate the chip. Simulation is just a guide to how the circuit will respond under one specific set of parameters… that I can guarantee you will never be seen in silicon exactly as it was modeled in simulation. It’s just a model! It’s kind of like trying to match two snowflakes. You will never find an actual chip that matches a given simulation to anything like 0.1%, yet people talk about 0.1% or better “accuracy” in SPICE. That’s nonsense.

So, that simulation that you are trying to make more “accurate”… if you think that tightening down on the RELTOL is going to make a difference… think again. Every simulation is just an idealized point in space! You can model the space in multiple dimensions by running process corners, parameter sweeps, and Monte Carlo but it’s still just a model of the potential operating space. Hopefully most of your silicon is going to live in that same space. If not, then you’ve got a real problem! The critical issue is to demonstrate that the simulation space covers your objective specs in such a way that you will get acceptable yield. And you can be assured that if you use a simulator that is identical to what your foundry uses to develop device models from the silicon, well… that’s as good as you can get.

What got me started on this topic today was an article I read over at SCDsource, which just has it completely dead wrong on the subject of simulator accuracy, by focusing on the infamous SPICE parameter known as RELTOL! I’ll leave it to you if you care to follow the link to find out where this came from, since I’d rather not repeat erroneous information here!

I think it’s critically important that analog designers not get sidetracked by claims of “SPICE accuracy”. That is all too often just another red herring. So here’s some irony for you… RELTOL has nothing to do with accuracy! RELTOL in SPICE simulators is a convergence control parameter! If you relax RELTOL you will get more numerical noise, if you tighten it up you will (hopefully) get less. That’s it! Which is why a loose RELTOL setting will show up as reduced SNR in something like an ADC simulation. None of it is real, it’s all just a numerical artifact.

DEFINITION:

RELTOL = x

Relative error tolerance allowed. (Default =.001 or .1%.). If the ratio of successive values in iteration are within RELTOL of one, this value is considered to have converged.

This definition, which you can find by following the RELTOL link above, says it all. But if you want another take on it, here’s how Ken Kundert described RELTOL in his book “The Designer’s Guide to SPICE and Spectre” (reference: K. Kundert, Springer; 1st edition: May 31, 1995, highlighting added by yours truly). I think that Ken and others have recognized that confusion over this topic is very common, since you can also find this excerpt on the Designers-Guide website:

Reducing reltol decreases the error in the results computed by the simulator, however no level of accuracy is guaranteed. Nor is any particular level of accuracy implied from a given value for reltol. In particular, setting reltol to 0.1% in no way implies that the accuracy attained by the simulator is 0.1%.

RELTOL only controls the amount of change in the values of node voltages that a simulator allows as it iterates from one point to the next. It’s all relative, and in this case it’s only relative to the value of the previous iteration. As Ken said, RELTOL has nothing to do with accuracy.

The key message is this and it goes for almost any product you buy, especially in EDA: Don’t get sidetracked by specmanship and red herrings.

Because ultimately, it’s not the simulator… it’s the silicon! If you don’t understand what a simulator control parameter does, please ask an expert. Don’t just “turn the knobs” like RELTOL hoping for a better result.

-Mike

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