Hello Everyone,
Many of you may be familiar with the slogan that was created by Bill Clinton’s presidential campaign manager in 1992 - “It’s the economy, stupid”! James Carville created that message to keep the Clinton campaign focused on what he felt was the real issue at the time, so that they wouldn’t get sidetracked. Since that slogan became so memorable it has been re-used and adapted many times, and I think it is very appropriate to keep a similar message in mind when you are doing SPICE or Fast-SPICE simulation of your IC design.
“It’s the silicon, ******!” NOT the simulation!
OK, now I certainly don’t want any of you to stop using simulation, but I need to make what I think is a very important point here. I see many people get sidetracked by focusing on (what they think is) simulation “accuracy” when they should be focusing on the real goal; how accurately is your simulator predicting the behavior of the silicon? There is a HUGE difference.
Every designer knows that you are going to see a distribution of performance when you fabricate the chip. Simulation is just a guide to how the circuit will respond under one specific set of parameters… that I can guarantee you will never be seen in silicon exactly as it was modeled in simulation. It’s just a model! It’s kind of like trying to match two snowflakes. You will never find an actual chip that matches a given simulation to anything like 0.1%, yet people talk about 0.1% or better “accuracy” in SPICE. That’s nonsense.
So, that simulation that you are trying to make more “accurate”… if you think that tightening down on the RELTOL is going to make a difference… think again. Every simulation is just an idealized point in space! You can model the space in multiple dimensions by running process corners, parameter sweeps, and Monte Carlo but it’s still just a model of the potential operating space. Hopefully most of your silicon is going to live in that same space. If not, then you’ve got a real problem! The critical issue is to demonstrate that the simulation space covers your objective specs in such a way that you will get acceptable yield. And you can be assured that if you use a simulator that is identical to what your foundry uses to develop device models from the silicon, well… that’s as good as you can get.
What got me started on this topic today was an article I read over at SCDsource, which just has it completely dead wrong on the subject of simulator accuracy, by focusing on the infamous SPICE parameter known as RELTOL! I’ll leave it to you if you care to follow the link to find out where this came from, since I’d rather not repeat erroneous information here!
I think it’s critically important that analog designers not get sidetracked by claims of “SPICE accuracy”. That is all too often just another red herring. So here’s some irony for you… RELTOL has nothing to do with accuracy! RELTOL in SPICE simulators is a convergence control parameter! If you relax RELTOL you will get more numerical noise, if you tighten it up you will (hopefully) get less. That’s it! Which is why a loose RELTOL setting will show up as reduced SNR in something like an ADC simulation. None of it is real, it’s all just a numerical artifact.
DEFINITION:
RELTOL = x
Relative error tolerance allowed. (Default =.001 or .1%.). If the ratio of successive values in iteration are within RELTOL of one, this value is considered to have converged.
This definition, which you can find by following the RELTOL link above, says it all. But if you want another take on it, here’s how Ken Kundert described RELTOL in his book “The Designer’s Guide to SPICE and Spectre” (reference: K. Kundert, Springer; 1st edition: May 31, 1995, highlighting added by yours truly). I think that Ken and others have recognized that confusion over this topic is very common, since you can also find this excerpt on the Designers-Guide website:
Reducing reltol decreases the error in the results computed by the simulator, however no level of accuracy is guaranteed. Nor is any particular level of accuracy implied from a given value for reltol. In particular, setting reltol to 0.1% in no way implies that the accuracy attained by the simulator is 0.1%.
RELTOL only controls the amount of change in the values of node voltages that a simulator allows as it iterates from one point to the next. It’s all relative, and in this case it’s only relative to the value of the previous iteration. As Ken said, RELTOL has nothing to do with accuracy.
The key message is this and it goes for almost any product you buy, especially in EDA: Don’t get sidetracked by specmanship and red herrings.
Because ultimately, it’s not the simulator… it’s the silicon! If you don’t understand what a simulator control parameter does, please ask an expert. Don’t just “turn the knobs” like RELTOL hoping for a better result.
-Mike
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SPICE simulation accuracy
analog
RELTOL
red herrings
EDA tools
I’m Mike Demler. My background includes 18 years designing analog integrated circuits, and more than 10 years in EDA where I am currently a Product Marketing Manager in Synopsys’s AMS Group. In my spare time, I also coach youth inline hockey.
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