Hi All,

You have probably heard a lot about multi-core and multi-threading being used to accelerate SPICE simulation over the past year or so. I know that this topic was of great interest during my own presentations at the recent Design Automation Conference. If you were not able to attend DAC, an upcoming web seminar will give you a great opportunity to learn more about how to accelerate HSPICE simulation by taking advantage of multi-core CPUs. Here is the registration info:

Get the Most Out Of Your HSPICE on Single & Multi-Core Computers
Accelerate Circuit Simulation with 2008 HSPICE!

Date: July 15, 2008,
Time: 11:00 am PT/2:00 pm ET
Duration: 60 minutes (including Q&A)
Hosted by EDN, sponsored by Synopsys

You can follow the link above to register for this online seminar, which will feature a live and hopefully very interactive session where you get to ask questions of the HSPICE R&D Team.

Come prepared to ask these experts whatever simulation questions are on your mind:

Dr. Kishore Singhal, Synopsys Scientist
Dr. Scott Wedge, Sr. Staff Engineer
Ted Mido, Sr. Staff Engineer
Harald Von Sosen - Principle Engineer

I will be off on vacation for the next two weeks. I hope that you are all enjoying a nice summer as well.

Aloha,

Mike
SPICE simulation
HSPICE
multi-core
multi-threading

Hi All,

After discovering the forthcoming workshop on Formal Verification of Analog Circuits, which I wrote about here last week, I found that another small workshop was held earlier this year to address “Designing Correct Circuits”. The Seventh International Workshop on Designing Correct Circuits (DCC) was held in March 2008 in Budapest, Hungary.

Fortunately, you can download the workshop proceedings if you are interested to learn more about some of the most forward-looking work that is going on in AMS verification. I found one paper particularly interesting and relevant to the discussion we carry on here, titled Some “Real World” Problems in the Analog and Mixed Signal Domains. The authors are Kevin D Jones, Jaeha Kim, and Victor Konrad - all of Rambus. You can find slides of their presentation starting on page 59 in the DCC proceedings.

If you have been reading my earlier posts, you will know that I couldn’t agree more with the “Real World” authors when they point out that analog and digital designers exist in fundamentally different worlds, which leads to the challenge of how analog meets digital in mixed-signal verification. There is a lot that can be learned by examining how verification is practiced in the digital domain. At the same time progress will not be made if we don’t understand that some (or perhaps most?) AMS problems are fundamentally different and require the development of new approaches to increase verification productivity and robustness. (See ... Because digital design is so easy! and Analog design is NOT black magic… but it is VERY hard).

I recommend downloading the DCC paper. Let me know if you come across any other interesting workshops, papers or research in the area of AMS verificaiton and I will be sure to share it here.

-Mike
Formal methods
AMS verification
analog circuits

Hello Everyone,

Some of you may be familiar with the concept of formal verification for digital circuits. If you look at the Wikipedia definition, you will see that formal verification is a process of “proving or disproving the correctness of intended algorithms underlying a system with respect to a certain formal specification or property, using formal methods of mathematics.” Phew!!!

Doesn’t sound like that would work for AMS circuits, does it? Digital designs can apply boolean logic to check that a design is “correct by construction”, but how would that work for analog/mixed-signal?

I just came across a small workshop that is being held in exactly two weeks, which focuses on exactly this topic. Papers are being presented by a small group that is actively working on the development of formal verification for analog. I’m wondering if any of you are familiar with this conference, especially if you have attended or are planning to attend. The workshop is part of the 20th International Conference on Computer Aided Verification, which is also new to me. Since I am an analog guy of course

Formal Verification of Analog Circuits (FAC) ‘08, A satellite workshop at CAV 2008, July 14th, 2008, Princeton, CT

A few of the topics to be presented:

1. Analog Property Checkers: A DDR2 Case Study K.D. Jones and V. Konrad (Rambus Inc. USA) D. Nickovic (Verimag, University of Grenoble, France)
2. Abstract Modeling and Simulation Aided Verification of Analog/Mixed-Signal Circuits S. Little and C. Myers (University of Utah, USA)
3. Statistical Model Checking of Mixed-Analog Circuits E. Clarke, A. Donze and A. Legay (Carnegie Mellon University, USA)
4. Invited talk: A Digital Verifier’s Peek into the Analog World
   Victor Konrad (Rambus Inc. USA)

The invited talk fits right in here with the topic of how analog meets digital in verification. Unfortunately, I will be on vacation so won’t be able to attend myself. (Hawaii or New Jersey…. hmm…)

If any of you do attend please let me know, since I think that our readers would be very interested in a report.

-Mike
formal verification
AMS verification

That was the question I asked attendees at the Synopsys AMS breakfast panel meeting at DAC on June 10. Let me say right up front that I am aware that self-selection bias can be a factor in surveys such as this, but I think you will find the results to be interesting nevertheless.

We have been hearing from several writers and self-described EDA experts lately, who have accused the EDA industry of lagging in providing solutions for analog design, claiming that analog design automation needs to “catch up” with digital design automation. By catch up here, they are referring to design implementation - which of course means the synthesis, place & route that is the basis of most digital design flows. I have written about these misconceptions of the non-cognescenti several times before, most recently in Does AMS need its own year?

So then, why did 75% of the participants in this survey say that Verification is the #1 issue versus only 13% for analog synthesis, and a meager 6% for AMS process migration? Perhaps because these folks are the cognescenti… the people who personally take on the challenges of AMS design and verification on a daily basis.

The population of respondents and their preferences is very telling, I think. We had a good mix of attendees; who described themselves as involved in either analog or digital design, verification engineers, CAD engineers, or other (such as CTOs, foundry engineers, analysts, etc.).

Of the self-described verification engineers 100% stated that AMS Verification was the #1 issue. One could argue that is no surprise, since the topic of the breakfast panel discussion was AMS Verification and Moore’s Law… solutions for 45nm and beyond. But, the survey did provide an opportunity to select “Other” as the greatest need, and nobody selected that option.

Looking at the response of designers in attendance, 86% of the analog designers said that AMS verification is their biggest issue. Now these are the people that would use analog synthesis or process migration tools, so I think that is especially significant. I believe that analog designers understand very well that process migration requires a lot more than re-sizing devices with some optimization algorithm. Topology changes are inevitably required when voltage levels drop and those stacked cascode structures no longer work - for example.

Digital designers also indicated that verification was the most important issue in AMS design, by an 80% majority. The chart that I showed in my last post, things heard at DAC - day 3, apparently rings true with the designers who know best what happens when analog meets digital.

Finally, the CAD engineers and managers chose AMS verification as the #1 issue by a 68% majority. It should come as no surprise that CAD engineers made up most of the small number of respondents who were interested in analog synthesis.

So… there you have it. What, in your opinion, is the single greatest need for enhanced EDA solutions in AMS design? As always, all responses and opinions are welcome.

-Mike
AMS verification
analog design
digital design
verification engineers
CAD engineers
Design Automation Conference
user surveys

• I am still hearing lots of positive feedback on the AMS Verification Breakfast that we held on Tuesday. It looks like we hit on the key issue effecting AMS design in this so-called “the Year for Analog”. Attendance at my suite presentation on A Methodology for Mixed-Signal Circuit Design & Verification with Discovery-AMS and Synopsys’ Custom Environment has been very high. Many attendees have said that they wish they could have attended the AMS breakfast, so please check back here to find out when we have the video replay up on the Synopsys website for viewing. It should take us about 30 days after DAC.

• From a customer at one of my suite presentations: “That is exactly the problem that we had at my company”! He was referring to this chart:

The chart shows that the problem of how analog meets digital is the major cause of chip failures as AMS content in SoCs continues to increase. The problem comes from analog and digital living in their own design & verification flows until it comes time to put the silicon together. It’s great to her that we are focusing on the right thing, and not some lesser issues that the non-cognescenti think represent progress in AMS.

-Mike
Design Automation Conference
AMS verification Verilog-AMS
analog
mixed-signal